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Series · 1 of 10 parts published

Silicon to Systems

A bottom-up tour of how computers actually work.

Most explanations of computer architecture stop at the abstraction you happen to need. This series goes the other direction — start from the physics of a single transistor and build up, one interactive simulator at a time, until we've assembled a working CPU. The goal is that by the end you can answer 'what is actually happening when my code runs?' from first principles, without hand-waving.

Progress10%
01

Logic Gates and Boolean Algebra

Published

The Foundation of Digital Computing

Transistors as switches, the seven basic gates, and the algebra that lets us reason about them. Interactive simulators for the transistor and each fundamental gate.

Read part 1
02

Adders and Arithmetic

Planned

From XOR to a working ALU

Half adders, full adders, ripple-carry vs. carry-lookahead, and an interactive 4-bit ALU you can run programs through.

03

Memory: Latches and Flip-Flops

Planned

State-holding circuits, explained visually

How gates with feedback become memory. SR latches, D latches, edge-triggered flip-flops, and a small interactive register file.

04

Clock and Sequencing

Planned

Synchronous logic and the heartbeat of a CPU

Why everything in a CPU happens on clock edges, what setup and hold times mean, and an interactive pipeline visualization.

05

A Tiny CPU

Planned

Putting it all together

Combine arithmetic, memory, and sequencing into a runnable 4-bit CPU. Type a tiny program; watch the registers and bus update cycle-by-cycle.

06

Caches and the Memory Hierarchy

Planned

Why your CPU lies about memory

Why memory is slow, what locality is, and an interactive cache simulator that shows hit/miss patterns for different access strategies.

07

Pipelining and Hazards

Planned

Making the CPU faster (and harder to reason about)

Instruction pipelines, data hazards, branch prediction. An interactive pipeline diagram with stalls and forwarding visualized.

08

Going Parallel

Planned

Cores, threads, and the cost of sharing

How multi-core changes the rules. Cache coherence protocols, memory ordering, and an interactive multi-core memory simulator.

09

The OS Layer

Planned

From bare metal to processes

Virtual memory, interrupts, system calls, and the boundary between hardware and the kernel.

10

GPUs and the Future

Planned

When the CPU isn't enough

How GPU architecture differs from CPUs, why ML workloads found their natural home there, and where things are heading.

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Interactive explainers for machine learning, statistics, and the systems behind them — built so each idea is something you can manipulate, not just read.

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